DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees


Design verification was on full display last week in Munich, Germany, as DVCon Europe offered two full days of more than 30 sessions. Attendees could choose from 16 tutorials, two panels, three keynotes and 16 technical presentations or wander through a small but active exhibit floor, with exhibitors that included OneSpin. The conference for engineers by engineers is meant to be educational,... » read more

Building Chips That Can Learn


The idea that devices can learn optimal behavior rather than relying on more generalized hardware and software is driving a resurgence in artificial intelligence, machine leaning, and cognitive computing. But architecting, building and testing these kinds of systems will require broad changes that ultimately could impact the entire semiconductor ecosystem. Many of these changes are wel... » read more

Customizable Apps – Avoiding The Pitfalls Of EDA Frameworks


For those of us involved with EDA tools in the late '80s and early '90s, the word “frameworks” brings back memories of rigid methodology and use models, coupled with CAD complexity. Cadence and Mentor, among others, proposed the EDA framework as a mechanism to provide design revision management coupled with tool flow control (I can already imagine your eyes glazing over). For some situat... » read more

Formal Has Its Day


As new technologies receive more mainstream attention, it is common for the experts in the area to provide a critical mass of enthusiasm. Formal is in this mode with multiple meetings throughout the year and around the globe. Perhaps one of the most successful of these is the annual Formal Day event put on by Test & Verification Solutions (TVS) based in the UK. This live and online event is... » read more

The Early Bird Catches The Bug Using Formal


It has been suggested that formal might replace simulation, at least in some parts of the design flow. Not likely! The question is, how can formal be layered on top of simulation flows to improve coverage and schedule? The way formal is being used at the larger semiconductor companies is evolving. In many of these companies a small team of hardcore formal experts are employed across differen... » read more

Planes, Cars, And Lagging Standards


Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

Everything You Wanted to Know About Formal, But Were Too Afraid to Ask


Formal Verification is one of those EDA technologies that's been used in mainstream development in one or two applications for many years. The true power of the approach only now has started to capture the attention of engineers. Although there are a few reasons for this, perhaps the most significant is formal’s ill-gotten reputation as a mysterious beast too difficult to tame. After worki... » read more

Can Cars Be Hack-Proof?


Not many days go by when there isn't a news headline describing the latest hacking attempt — or success — of an automobile or automotive system. Malicious hacking has been around almost since the dawn of connected electronics, but it's happening with increasing sophistication in the automotive sector. Even high-end vehicles suffer security flaws that are too costly or not worthwhile to f... » read more

The Week In Review: Design/IoT


Tools Cadence updated its Allegro PCB product line with a new manufacturing option that accelerates manufacturing documentation and technology updates for increased efficiency, control and productivity for designers and streamlining handoff to manufacturing. The release also allows users to develop custom fabrication and assembly rules. Invionics expanded its Invio EDA development platfor... » read more

Formal Verification 101


By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more