Deploying Multi-Beam Mask Writers

Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss the company’s deal with Intel, photomasks, multi-beam mask writer technology and other topics. What follows are excerpts of that conversation. SE: This has been a significant year for IMS for two reasons. First, Intel recently announced plans to acquire IMS. Second, at the recent ... » read more

7nm Fab Challenges

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Multi-Beam Market Heats Up

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market. In one surprising move, [getentity id="22846" e_name="Intel"] is in the process of acquiring IMS Nanofabrication, a [gettech id="31058" t_name="multi-beam e-beam"] equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer t... » read more

Taming Mask Metrology

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Mask Metrology Challenges Grow

Photomasks are becoming more complex at each node. In fact, masks are moving from traditional shapes to non-orthogonal patterns and complex shapes, such as curvilinear mask patterns. To measure patterns and shapes on the mask, photomask makers use traditional critical-dimension scanning electron microscopes (CD-SEMs). In general, the CD-SEM, the workhorse metrology tool in the mask shop, use... » read more

Mask Supply Chain Preps For 10nm

As the semiconductor industry gears up for the 10nm logic node—now likely to begin in the second half of 2017—the photomask supply chain is preparing to grapple with the associated challenges, including dramatic increases in photomask complexity, write times and data volumes. The 10nm node will require more photomasks per mask set, the ability to print smaller and more complex features, ... » read more

Challenges Mount For Patterning And Masks

Semiconductor Engineering sat down to discuss [getkc id="80" comment="lithography"] and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief execu... » read more

Is Multi-Patterning Good for You?

I think we can all remember growing up and our parents making us take nasty-tasting medicines, or eat foods we didn’t like, or endure painful things like shots, all under the banner of “It is good for you!” We didn’t like it then, and we still don’t like it as adults. We would all prefer a way to lose weight while eating anything we want, or building strong muscles and aerobic health ... » read more

Stopping Mask Hotspots Before They Escape The Mask Shop

By Aki Fujimura The same types of physics-based issues that have haunted lithography for decades have started to impact mask writing as well. The increasingly small and complex mask shapes specified by optical proximity correction (OPC) that are now required for faithful wafer lithography at 28nm-and-below nodes have given rise to an increase in mask hotspots. Mask hotspots occur when the shap... » read more

A Guide To Advanced Process Design Kits

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

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