Application Of Overlay Modeling And Control With Zernike Polynomials In An HVM Environment

By JawWuk Ju, MinGyu Kim and JuHan Lee of SK Hynix; Jeremy Nabeth, John C. Robinson and Bill Pierson of KLA-Tencor; and Sanghuck Jeon and Hoyoung Heo of KLA-Tencor Korea. Abstract Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field... » read more

Device Overlay Method For High-Volume Manufacturing

By Honggoo Lee, Sangjun Hana and Youngsik Kima of SK Hynix; Myoungsoo Kim, of the Department of Semiconductor System Engineering at Korea University; Hoyoung Heo, Sanghuck Jeon and DongSub Choi, KLA-Tencor Korea; and Jeremy Nabeth, Irina Brinster, Bill Pierson, and John C. Robinson of KLA-Tencor. Abstract Advancing technology nodes with smaller process margins require improved photolithogra... » read more

7nm Lithography Choices

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm. Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies ... » read more

Getting Over Overlay

Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down. So what’s causing the slowdown? Or for that matter, what could ultimately undo [getkc id="74" comment="Moore's Law"]? It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And ov... » read more