tag: parasitic extraction

Top Tech Talks Of 2018
By Linda Christensen - 31 Dec, 2018 - Comments: 0

2018 shaped up to be a year of transition and inflection, sometimes in the same design. There were new opportunities in automotive, continued difficulties in scaling, and an explosion in AI and machine learning everywhere. Traffic numbers on stories give a snapshot of the most current trends, but with videos those trends are even more apparent because of the time invested in watching those v... » read more

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results
By Yousry ElMaghraby - 20 Dec, 2018 - Comments: 0

There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

The Process Design Kit: Protecting Design Know-How
By John Ferguson - 08 Nov, 2018 - Comments: 2

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each company. In these days, when designs contained hundreds of transistors, companies modeled each feature in an IC at a first principles level, meaning each transistor or fundamental device was analyzed an... » read more

3D Extraction Necessities For 5nm And Below
By Ruben Molina - 25 Jan, 2018 - Comments: 0

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more impo... » read more

Massively Parallel Electrically Aware Design
By Cadence - 26 Oct, 2016 - Comments: 0

In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server ar... » read more

Calibre xACT Parasitic Extraction Supports Signal Integrity At Advanced Nodes
By Mentor, a Siemens Business - 21 Apr, 2016 - Comments: 0

At advanced nodes, signal integrity analysis requires precise characterization, which in turn requires an accurate extracted netlist. Models that handle new impacts on parasitic extraction at advanced nodes, including multi-patterning, finFETs, and resistance and capacitance effects, must be used. Learn how the Calibre xACT extraction tool supports these advanced foundry device models and leadi... » read more

Next-Generation Parasitic Extraction For 16nm And Beyond
By Mentor, a Siemens Business - 21 May, 2015 - Comments: 0

Advanced nodes and innovative process features such as finFET transistors require a leap forward in the performance and accuracy of analysis tools. The new Calibre xACT solution is a high-performance, high-accuracy parasitic extraction tool architected from the top-down for diverse IC design styles at advanced nodes. The Calibre xACT product delivers reference-level accuracy for leading-edge fi... » read more

How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool
By Cadence - 19 Nov, 2014 - Comments: 0

Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges,... » read more

Advanced Nodes Drive Changing EDA Requirements
By Ann Mutschler - 23 Oct, 2014 - Comments: 0

With new technical requirements of today’s bleeding edge manufacturing processes propelling the ecosystem of semiconductor foundries, EDA tool suppliers and IP developers, work is being done behind the scenes like a well-conducted orchestra to make sure customer designs can flow through a foundry when the time comes. One of the areas in the design process where new processes are felt acute... » read more

The Week In Review: Design
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy