Addressing Memory Characterization Capacity And Throughput Requirements With Dynamic Partitioning

Typical memory characterization techniques using memory compilers and instance-specific memories have a number of tradeoffs—development time, accuracy, performance, and more. Ad-hoc instance-specific characterization methods such as dynamic simulation, transistor-level static timing analysis, and divide-and-conquer suffer from multiple limitations that prohibit usage for 40nm technologies and... » read more

Team Work

While I am not much of a golf player, I participated in a golf tournament over the summer. It was a very friendly setup with teams of four playing against each other. Each player of the team hits his ball, and the ball that lands in the best position determines the starting point for every one of the team for the next stroke. The fact that only the best shot of the team counts, definitely ma... » read more

Hierarchy And Pain Management

By Bernard Murphy Hierarchy is unavoidable for any large design. It partitions development and verification complexity into digestible chunks. It enables parallel development on different parts of a system. It promotes reuse. And it provides a graceful method to partition for implementation. And yet, there are times when hierarchy gets in the way. The biggest drawback with hierarchy is that... » read more

Experts At The Table: Latency

By Ed Sperling Low-Power/High-Performance engineering sat down to discuss latency with Chris Rowen, CTO at Tensilica; Andrew Caples, senior product manager for Nucleus in Mentor Graphics’ Embedded Software Division; Drew Wingard, CTO at Sonics; Larry Hudepohl, vice president of hardware engineering at MIPS; and Barry Pangrle, senior power methodology engineer at Nvidia. What follows are exce... » read more