Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Advantages Of Designing With PCI Express 4.0 Draft 0.7 And PIPE 4.4 Specifications


Due to the PCI Express (PCIe) specification’s many benefits such as reliability, low-power, latency and scalable bandwidth from 2.5GT/s to 16GT/s, it has evolved to become ubiquitous in designs for a wide range of applications. The recent release of PCIe 4.0 Draft 0.7 specification to PCI-SIG members and availability of the Physical Interface for PCI Express (PIPE) specification has renewed u... » read more

Five Pitfalls In PCIe-Based NVMe Controller Verification


Non-Volatile Memory Express (NVMe) is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe-based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and ... » read more

An Easier Path To Faster C With FPGAs


For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

Can IP Integration Be Automated?


What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

Top 15 Integrating Points In The Continuum Of Verification Engines


The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

One PHY Does Not Fit All


Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

Blog Review: April 15


How much memory do you need to look 13 billion years in the past? Rambus' Aharon Etengoff ponders the Square Kilometre Array's massive number of radio telescopes and what it means for computing. NXP's Martin Schoessler argues that for smart cities to work for their citizens, both technology companies and government entities will need a new mind-set. Reinventing the wheel is a good thing i... » read more

The Week In Review: Design/IoT


Tools Cadence rolled out a use-case scenario verification tool that automates some test development that has been done manually in the past. The new tool accelerates development of software-driven tests and debug to ferret out complex SoC-level bugs. Cadence claims a 10X productivity improvement. Mentor Graphics uncorked a new version of its verification IP for PCI Express. The new IP decre... » read more

Optimizing Analog For Power At Advanced Nodes


As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

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