Blog Review: April 4


Synopsys' Richard Solomon explains PCIe's upstream and downstream component naming and why understanding the perspective is key. Mentor's Cristian Filip dives into frequency domain analysis for high data rate SerDes links and the movement toward a simpler way of channel characterization. Cadence's Paul McLellan takes a look at the history of the RISC processors and the death of microcode ... » read more

32GT/s PCI Express Design Considerations


Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces


As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Memory Test Challenges, Opportunities


The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

Targeting And Tailoring eFPGAs


Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

CCIX – What And Why?


There are two significant issues with today’s I/O interconnects: high speed storage and networking applications need more bandwidth than currently available technologies provide, and co-processing/acceleration functions need cache coherency for faster access to memory in heterogeneous multi-processor systems. These requirements are driving the development of a new specification called Cache C... » read more

The Week In Review: IoT


Deals Advanced Semiconductor Engineering was selected by zGlue as its strategic manufacturing partner. The ASE Group will make the zGlue Integrated Platform, which is said to enable customization for consumer and industrial IoT markets. The ZiP integrates hardware and software in a modular 3DIC-based platform. ASE will assemble zGlue-certified chiplets for connecting through zGlue Smart Fabric... » read more

A Tale of Two Testers


David Tacelli, president and CEO of Xcerra, was excited. His company’s reception for customers (and the press) at the Trou Normand restaurant in San Francisco’s hip South of Market neighborhood was going very well. Gourmet salames and other tasty foods were on offer, along with fine wines and craft ales and beers. He gleefully pointed out to editors that the product to be introduced at t... » read more

CCIX Enables Machine Learning


It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

Come Together Right Now Over… Virtual Prototypes


As a frequent traveler and gadgets enthusiast I love the concept of all my devices being connected. However, more often than not I experience a divide which is sometimes caused by bad software and sometimes caused by missing hardware interfaces. My recent frustration was related to my tablet missing a USB port to upload new maps to my GPS device. The GPS device became a divided, isolated pi... » read more

← Older posts