Overcoming The Limits Of Scaling

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

The Zen Of Processor Design

Mark Papermaster, chief technology officer at Advanced Micro Devices, sat down with Semiconductor Engineering to discuss how to keep improving performance per watt, new packaging options, and the increasing focus on customization for specific tasks. What follows are excerpts of that conversation. SE: As we get more into the IoT and we have to deal with more data, not to mention cars where da... » read more

How Do We Get To Full Throttle In Mobile?

By Govind Wathan and Brian Fuller With each new generation of mobile device, we look forward to running the latest apps—especially games. (It's amazing how immersive mobile games have become in just a few years). We’re consumers but we’re also engineers, and here we’re faced with a huge challenge. It’s not just the games that get more powerful. A whole new generation of virtual ... » read more

No More Straight Lines

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

System-Level Verification Tackles New Role

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

2.5D Becomes A Reality

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Optimizing DDR Memory Subsystem Efficiency

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

Shifting Performance Bottlenecks Driving Change In Chip And System Architectures

The rise of personal computing in the 1980s — along with graphical user interfaces (GUIs) and applications ranging from office apps to databases — drove the demand for faster chips capable of removing processing bottlenecks and delivering a more responsive end-user experience. Indeed, the semiconductor industry has certainly come quite a long way since IBM launched its PC way back in 1981. ... » read more

Gaps In Performance, Power Coverage

The semiconductor industry always has used metrics to define progress, and in areas such as functional verification significant advances have been made. But so far, no effective metrics have been developed for power, performance, or other system-level concerns, which basically means that design teams have to run blind. On the plus side, the industry has migrated from the use of code coverage... » read more

Power, Standards And The IoT

Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

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