Why All Nodes Won’t Work


A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

Zen And The Art Of Network Timestamping


Network devices, namely switches and routers, are used for forwarding data packets from their source to their destination - or at least that is what they are meant to do. In practice, these devices tend to do a lot more than that. They can be involved in Quality of Service (QoS) enforcement, filtering, load balancing, fault detection, performance measurement, event logging and various other act... » read more

Pushing Performance Limits


Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

7/5nm Timing Closure Intensifies


Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Warp Speed Ahead


The computing world is on a tear, but not just in one direction. While battery-powered applications are focused on extending the time between charges or battery replacements, there is a whole separate and growing market for massive improvements in speed. Ultimately, this is where quantum computing will play a role, probably sometime in the late 2020/early 2030 timeframe, according to multipl... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns


In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

Advanced Packaging Still Not So Simple


The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

Tech Talk: eFPGA LUTs


Cheng Wang, Flex Logix's senior vice president of engineering, explains how to use lookup tables in embedded FPGAs and which number of inputs is best for which application. https://youtu.be/ScnIbCOLcP4 » read more

Tech Talk: TCAM


Dennis Dudeck, IP solutions FAE at eSilicon, talks about how to save power and area with ternary content addressable memory. https://youtu.be/y1FhdoNdzOw » read more

Extracting Maximum Performance From Hardware


The Arm DS-5 Streamline performance analyzer provides system performance metrics, software tracing, and statistical profiling to help engineers get the most performance from hardware and find important bottlenecks in software. The Raspberry Pi 3 is one of the easiest systems for learning Streamline, and a quad-core Cortex-A53 also makes it a good target for learning Linux development. Many o... » read more

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