tag: PHY

MIPI Deployment In Ultra-Low-Power Streaming Sensors
By Mixel - 13 Mar, 2024 - Comments: 0

Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption if not conceived and executed carefully. A device like a high-resolution, high-frame-rate home security camera in a non-wired application requiring frequent battery changes or recharging will likely... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes
By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization
By proteanTecs - 11 Oct, 2022 - Comments: 0

Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers
By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Integrated Ethernet PCS And PHY IP For 400G/800G Hyperscale Data Centers
By Priyank Shukla - 09 Sep, 2021 - Comments: 0

Ethernet has become the primary network protocol of choice for the required server-to-server communication in hyperscale data centers, as it allows hyperscalers to disaggregate network switches and install their software operating systems independently. Ethernet enables cost-effective, dense, open switches and networking technologies which reduce cost/power per bit with transistor scaling. Ethe... » read more

Will Automotive Ethernet Win?
By Bryon Moyer - 02 Sep, 2021 - Comments: 2

As internal combustion engines are replaced by electric motors, and mechanical linkages increasingly replaced by electronic messaging, an in-vehicle network is needed to facilitate communication. Ethernet, amended for automotive and other time-sensitive applications, appears to be the network of choice. But is that choice a done deal? And will Ethernet replace all other in-car networks? The ... » read more

Best 112G SerDes IP Architecture
By Manu Verma - 08 Jul, 2021 - Comments: 0

Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

112G SerDes Modeling And Integration Considerations
By Priyank Shukla - 14 Jan, 2021 - Comments: 0

The ever-increasing demand for compute power and data processing in accelerators, intelligence processing units (IPUs), GPUs, as well as training and inference SoCs is driving the adoption of 112G SerDes PHY IP solutions. Ensuring a reliable Ethernet link and efficient integration are the most essential requirements that designers need to meet. IBIS-AMI modeling can help predict SerDes link per... » read more

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