A Broad, Effective Approach to Optimizing for Power


As an industry we talk a lot about the challenges of power-aware design and accompanying issues at leading-edge nodes. There’s no denying some tough challenges, but if we’re honest, there are plenty of opportunities we can exploit right now to improve power in our designs. You’ve heard the saying, “death by a thousand cuts?” Well, when it comes to grappling with power in today’s ... » read more

FinFET Impacts For Reducing Physical IP Power Consumption


FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more