Post-Silicon Validation Using Formal Analysis


Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

Enabling Test Portability With Graphs


Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more