DDR4 Board Design And Signal Integrity Verification Challenges


This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching ... » read more

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP


Mobile systems require increasing data volume for multiple chip-to-chip interfaces. The high-speed MIPI® M-PHY is tailored for mobile systems where performance, power, and efficiency are key criteria. With up to 5,824 Mbps bandwidth, the speed meets devices’ high bandwidth and scalability requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications ... » read more

The Power Game


By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

Too Hot To Handle


By Ann Steffora Mutschler It used to be that a device could be designed to a thermal design power. The worst case power scenario would be imagined, and the device would be designed with that in mind. But those good old days are gone. Especially for consumer devices, how a device is going to behave with respect to time, or how people are going to use it, must be understood as completely a... » read more

The Double Whammy


By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more