The Journey To Exascale Computing And Beyond


High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

Supercomputing Efficiency Lags Performance Gains


In last month’s article, Top 500: Frontier is Still on Top, I wrote about the latest versions of the Top500 and Green500 lists. Power is an incredibly important aspect of designing a world performance leading supercomputer. (Why, I can remember back to when you could run the world’s fastest machine on only a couple MW of power.) The first Green500 list was published back in 2013. Happy 1... » read more

A Highly Wasteful Industry


The systems industry as a whole is not concerned about power. I know that is a bold statement, but I believe it to be true. The semiconductor industry is mildly concerned, but only indirectly. They care about power because thermal issues are limiting the functionality they can squeeze onto a chip, or in a package. Some users, such as data center operators, claim to care about power because i... » read more

How The Electronics Industry Can Shape A More Sustainable, Energy-Efficient World


By Piyush Sancheti and Godwin Maben We’re already experiencing the effects of our world’s changing climate—devastating wildfires, prolonged droughts, torrential flooding, just to name a few examples. Global energy consumption is increasing, raising carbon dioxide levels and triggering extreme weather conditions. Two key forces driving these trends are the shift to hyperscale datacenter... » read more

Efficient Gated Clock Design Approach for LFSR


A technical paper titled "A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers" was published by researchers at Università degli Studi di Catania, Italy. Abstract "This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respec... » read more

Accelerating IoT Designs: Designing For Low Power In The Era Of Smart Everything


Most of us have become accustomed to interacting with the ubiquitous technology ecosystem daily (if not hourly). From fitness trackers, smart vacuums, and semi-autonomous vehicles to the smart home devices that wake us up every morning, there’s no denying that the internet of things (IoT) boom has proliferated in every aspect of our lives. At the core of this instant, at-our-fingertips conn... » read more

Designing for FPGA Accelerators


This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

AI Power Consumption Exploding


Machine learning is on track to consume all the energy being supplied, a model that is costly, inefficient, and unsustainable. To a large extent, this is because the field is new, exciting, and rapidly growing. It is being designed to break new ground in terms of accuracy or capability. Today, that means bigger models and larger training sets, which require exponential increases in processin... » read more

Distilling The Essence Of Four DAC Keynotes


Chip design and verification are facing a growing number of challenges. How they will be solved — particularly with the addition of machine learning — is a major question for the EDA industry, and it was a common theme among four keynote speakers at this month's Design Automation Conference. DAC has returned as a live event, and this year's keynotes involved the leaders of a systems comp... » read more

Review of Bumpless Build Cube Using Wafer-on-Wafer & Chip-on-Wafer for Tera-Scale 3D Integration


New research paper titled "Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)" from researchers at Tokyo Institute of Technology and others. Abstract "Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bum... » read more

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