tag: power integrity

Thermal Challenges In Advanced Packaging
By Ed Sperling - 02 Dec, 2019 - Comments: 2

CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Addressing Pain Points In Chip Design
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Multiphysics Simulations for AI Silicon to System Success
By Ansys - 09 Oct, 2019 - Comments: 0

Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed de... » read more

Delivering High-Speed Communications: The Back Story
By Mike Gianfagna - 30 May, 2019 - Comments: 0

Back in January, I posted a blog about what it takes to deliver high-speed communication. In that post, I talked about a new test board for our high-speed 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes. We collaborated with several companies to build a high-precision board that could be used to test our SerDes in a system context. At that time, we were just finishing the opening act for thi... » read more

Engineering The Signal For GDDR6
By Shawn Nikoukary - 09 May, 2019 - Comments: 0

DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

2.5D, 3D Power Integrity
By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

The Week In Review: Design
By Jesse Allen - 23 Mar, 2018 - Comments: 0

M&A Synopsys acquired Silicon and Beyond, a provider of high-speed SerDes and ADC/DAC IP. The company was founded in 2012 as SilabTech and headquartered in Bangalore. Synopsys highlighted the team of R&D engineers with high-speed SerDes expertise that would be joining with the acquisition. Terms of the deal were not disclosed. ANSYS will acquire OPTIS, a provider of software for sci... » read more

In-Design Rail Analysis Is A Beautiful Thing
By Kenneth Chang - 22 Mar, 2018 - Comments: 0

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

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