Time For A DDR Background Check


In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

Power, Standards And The IoT


Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

IP Power Models Enable Energy-Aware System-Level Design


Energy efficiency is one of the primary design metrics for heterogeneous multi-core mobile platforms, and the very real threat of dark silicon reinforces the fact that we must manage energy consumption in these platforms intelligently. The way in which a platform is used absolutely determines how much energy it consumes, so we need to take a holistic approach to energy management. Furthermo... » read more

Experts At The Table: Improving The Efficiency Of Software


By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Dueling Power Formats


By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

Experts At The Table: Verification At 28nm And Beyond


Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE: Power seems to... » read more