tag: power reduction

Reducing Power In Data Centers
By Ed Sperling - 16 Jan, 2024 - Comments: 0

The rollout of generative AI, coupled with more data in general, is requiring data centers to run servers harder and longer. That, in turn, is generating more heat and accelerating aging, and to ensure these systems continue working over their projected lifetimes, chipmakers are building extra margin into chips. That increases the amount of energy required to run and cool them, and it can short... » read more

Holistic Power Reduction
By Brian Bailey - 11 May, 2023 - Comments: 0

The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient. Tools and methodologies are in place for most of the power-saving opportunities, from RTL down through implementation, and portions of the semiconductor industry already a... » read more

Evolving LTE Brings New Era Of Connectivity To IoT
By David Maidment - 12 May, 2016 - Comments: 0

The Internet of Things is here and ramping deployment today, but there’s still considerable work underway to optimize many aspects of the network. Not the least of this are the access technologies that exist or are emerging to enable the ‘last mile’ connectivity for IoT connected objects. Wireless access broadly fits into two main areas: licensed band and unlicensed band. Short-range unli... » read more

Power Reduction At RTL: Data Gating Adders And Multipliers
By Rob Eccles - 20 Apr, 2015 - Comments: 0

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings. One technique that is frequently used is the data gating of adders and m... » read more

Another Tool In The Bag
By Ann Mutschler - 06 Nov, 2014 - Comments: 0

Clocks can account for 25% to 40% of total dynamic power consumption in a complex chip, so when looking for areas to reduce power, the clock tree network is a good place to start. Structurally, it is certainly possible to have single-bit flip flops with a clock that connects to every one of the flip flops, and the power in general is proportional to the number of buffers in the clock tree on... » read more

Memory Power Reduction In SoC Designs Using PowerPro MG
By Various Writers - 07 May, 2014 - Comments: 0

Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50% to 70% of the power dissipation. We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories. To ... » read more

Reducing And Optimizing Power
By Ann Mutschler - 03 Mar, 2014 - Comments: 0

While power optimization/reduction techniques such as clock gating do help engineering teams improve designs from a power perspective, more can be done. In fact, there are tools and methodologies under development to incorporate power in a more meaningful way. Part of that involves accurately pinpointing what designers should be looking for. “If you look at academia or research that has... » read more

Schedule Versus Specifications
By Ann Mutschler - 14 Feb, 2014 - Comments: 0

With power being paramount in SoCs today, I was surprised to hear the amount of time spent on power reduction exercises can be only a few days. According to William Ruby at Ansys/Apache, how much time engineers spend on power reduction activities depends on how sensitive the design is to power and whether they are still trying to meet the power spec or -- based on the early power estimates �... » read more

Power Resolutions For 2014
By Mark Baker - 16 Jan, 2014 - Comments: 0

As the ball dropped at midnight in New York’s Time Square, signifying the beginning of 2014, many had already decided on their resolutions for the New Year. Others decide during the first few days of the New Year. Undoubtedly, consideration involves common resolutions that we fall back on year after year. Individuals might think about health, losing weight and becoming more fit. Others think ... » read more

How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs
By Various Writers - 15 Jan, 2014 - Comments: 0

Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines ... » read more

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