Package Modeling Needs For A Robust IC Power Integrity Sign-Off


Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Tech Talk: Power Sign-Off


Calvin Chow, area technical manager at Ansys, talks about power sign-off for complex SoCs at advanced nodes, including early stage prototyping, the importance of context, accurate power modeling of sub-blocks, and simulation of power-delivery networks. [youtube vid=MN4TjZ3dHVk] » read more

The Week In Review: Design


Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

System-Aware SoC Power, Noise And Reliability Sign-off


In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

What’s Wrong With Power Signoff


Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

FinFET-Based Designs: Power Sign-off Considerations


FinFET devices can operate at ultra-low sub-1V nominal supply voltage levels without impacting their delays. This allows for low power, higher performance designs needed for many of todays’ applications. These devices also have considerably higher drive strengths, allowing faster operating speeds. However, this can result in more localized di/dt current scenarios, and when coupled with more r... » read more

System-Aware SoC Power, Noise And Reliability Sign-off


In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

The Path To Power Signoff Is Getting Longer


Signoff on power used to be a fairly simple check-the-box kind of activity. Even if power budgets weren’t exactly met, they could usually be fixed in future iterations of a chip, whether that involved derivatives or new revs of the same chip. A number of things have changed since the much simpler days of 45/40nm and above, however. Power is now a market differentiator. In many cases, i... » read more

Technologies For Power, Signal, Thermal, And EMI Sign-Off


This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines. To download this white paper, click here. » read more