Power Limits Of EDA

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Power/Performance Bits: Oct. 4

Solar battery Chemists at the University of Wisconsin–Madison and the King Abdullah University of Science and Technology in Saudi Arabia integrated solar cells with a large-capacity battery in a single device that eliminates the usual intermediate step of making electricity and, instead, transfers the energy directly to the battery's electrolyte. The team used a redox flow battery, or R... » read more

Think Globally, Act Globally

For the last several months, I’ve been working on a series of articles about sustainable manufacturing in the semiconductor industry. How can we, as an industry, reduce our environmental footprint? It’s a big topic, and it’s been challenging to find concrete examples of ways fabs can reduce power consumption, water consumption, and greenhouse gas emissions. I’ll address these topics in ... » read more

Managing Power Without Impacting Design Intent

The good news is that there are many techniques available to optimize power in your design. The not-so-good news? Many of these power management techniques also create new complexities in the physical and functional behavior of electronic designs. Fortunately, there’s more good news: implementing a power-aware verification methodology can help you verify power optimization without detracti... » read more

Hitting The Power Integrity Wall At 10nm

At 10nm and beyond, the breakdown of some historic trends tied to Moore's Law is making it harder to fully harvest the benefits of scaling semiconductor technologies. Underlying the power, performance and area benefits of scaling are technological challenges that must be solved in order to make the semiconductor products a profitable business. Power-related challenges are among the most pres... » read more

Power Confounds, Challenges

I have to admit I’m always surprised to hear that design teams are not using tools to the fullest extent possible, leaving valuable power saving opportunities on the table, until I remember how daunting it is to get it all right without tremendous experience, expertise, and the right tools. I’m also always fascinated to learn about less-obvious effects from power. To this point, Aveek... » read more

Better PMIC Design Using Multi-Physics Simulation

Energy efficiency and thermal management are gaining importance in the IC and system design community. Because the integrated circuit is the major source of power consumption and hence heat dissipation, semiconductor companies are under immense pressure to reduce the overall power envelope of the IC that goes into the system. This phenomenon is seen globally, irrespective of whether the chip... » read more

Power To The People (Right On…)

If you’re the right age (or older), you will immediately think of John Lennon when you read the title of this piece.  The song was released in 1971, so I will cut many of you some slack on that. The title was inspired by several pieces of research that I was fortunate enough to be exposed to this past week. I am currently in Vancouver, British Columbia at the NEWCAS conference. NEWCAS... » read more

The Road To 5nm

There is strong likelihood that enough companies will move to 7nm to warrant the investment. How many will move forward to 5nm is far less certain. Part of the reason for this uncertainty is big-company consolidation. There are simply fewer customers left who can afford to build chips at the most advanced nodes. Intel bought Altera. Avago bought Broadcom. NXP bought Freescale. GlobalFoundrie... » read more

No More Straight Lines

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

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