Executive Insight: Jack Harding


[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

Industry Road Map Under Construction


While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

Tech Talk: Configurable Logic


Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

Explosion Of Creativity


One of Steve Jobs' great revelations occurred while watching his young daughter use a computer with a graphical user interface. He observed that adults ask how to use a computer, whereas children ask what you can do with it. The semiconductor industry is experiencing one of those seminal moments with the Internet of Things/Internet of Everything. While work continues to ensure that electrons... » read more

Rethinking Power


Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

How To Achieve Optimal PPA And Up To 10X TAT Gain In Your Next Digital Design Implementation


For complex, advanced-node designs, there’s a tug-of-war brewing between oft-conflicting goals around performance, power, and area (PPA) and turnaround time (TAT). Both are important for design success, yet it can be difficult to achieve optimal PPA with the highest productivity—without making any tradeoffs. At the root of this problem is that with traditional place-and-route tools, designe... » read more

Tech Talk: Set-Top Power


Broadcom's John Redmond, associate technical director for digital video technology, talks with Semiconductor Engineering about what the next-generation set-top boxes will look like and how they will save power. The video was shot at Cadence's Low Power Summit. [youtube vid=Ov2GFrUTzts] » read more

What Will Change In Design For 2015?


This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Pushing The Performance Boundaries Of ARM Cortex-M Processors For Future Embedded Design


One of the toughest challenges in the implementation of any processors is balancing the need for the highest performance with the conflicting demands for lowest possible power and area. Inevitably, there is a tradeoff between power, performance, and area (PPA). This paper examines two unique challenges for design automation methodologies in the new ARM Cortex-M processor: How to get maximum per... » read more

How To Reduce Implementation Headaches In FinFET Processes


In this era of compressed market windows and shrinking or changing technology, today’s engineers are always looking for ways to improve their overall product performance, power and area (PPA), while also decreasing their SoC design effort. The goal is to ease time-consuming and labor-intensive implementation tasks that will yield a reduction in design time, without sacrificing accuracy and op... » read more

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