Full-Chip Power Integrity And Reliability Signoff


As designs increase in complexity to cater to the insatiable need for more compute power — which is being driven by different AI applications ranging from data centers to self-driving cars—designers are constantly faced with the challenge of meeting the elusive power, performance and area (PPA) targets. PPA over-design has repercussions resulting in increased product cost as well as pote... » read more

Tech Talk: TCAM


Dennis Dudeck, IP solutions FAE at eSilicon, talks about how to save power and area with ternary content addressable memory. https://youtu.be/y1FhdoNdzOw » read more

I Say ‘High’ [Performance], You Say ‘Low’ [Power]


“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

Architect Specs Harder To Follow


Interpreting and implementing architects' specifications is getting harder at each new process node, which is creating problems throughout the design flow, into manufacturing, and sometimes even post-production. Rising complexity and difficulties in scaling have pushed much more of the burden onto architects to deal with everything from complex power schemes, new packaging approaches, and to... » read more

Executive Insight: Jack Harding


[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

Industry Road Map Under Construction


While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

Tech Talk: Configurable Logic


Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

Explosion Of Creativity


One of Steve Jobs' great revelations occurred while watching his young daughter use a computer with a graphical user interface. He observed that adults ask how to use a computer, whereas children ask what you can do with it. The semiconductor industry is experiencing one of those seminal moments with the Internet of Things/Internet of Everything. While work continues to ensure that electrons... » read more

Rethinking Power


Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

How To Achieve Optimal PPA And Up To 10X TAT Gain In Your Next Digital Design Implementation


For complex, advanced-node designs, there’s a tug-of-war brewing between oft-conflicting goals around performance, power, and area (PPA) and turnaround time (TAT). Both are important for design success, yet it can be difficult to achieve optimal PPA with the highest productivity—without making any tradeoffs. At the root of this problem is that with traditional place-and-route tools, designe... » read more

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