Interconnect Challenges Rising

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Back-End-of-Line (BEOL) Metallization

Physical Vapor Deposition (PVD) for Back-End-of-Line (BEOL) metallization is being pushed to the limits at the 16-nanometer (nm) technology node and beyond. Extending PVD for metal liner and barrier seed deposition is forcing the process into a narrow window that must be characterized prior to manufacturing introduction. Furthermore, understanding the liner dependency on the trench and via etch... » read more

The Trouble With MEMS

The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analo... » read more

Surprises At SEMICON West

As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about. Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that are driving growth and excitement at semiconductor equipment... » read more

Extending The Hardmask

In chip production, the backend-of-the-line (BEOL) is where the critical interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips. “The scaling roadblocks that the interconnect faces need to ... » read more

Will 7nm And 5nm Really Happen?

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

Interconnect Challenges Grow

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Manufacturing Bits: July 16

Photon Chips Harvard University, the Massachusetts Institute of Technology (MIT) and the Vienna University of Technology have devised an all-optical transistor controlled by a single photon. The optical transistor could enable the development of photonic quantum gates and deterministic multi-photon entanglement. For years, researchers have been looking to develop an optical transistor, whe... » read more

Trickle Down Equipment Economics

By Jeff Chappell By now, with the rise of China as a center of manufacturing, everyone in the chip industry has no doubt heard of the supposed Chinese curse, "May you live in interesting times." It's practically cliché. The thing is, the next two industry cycles may indeed prove interesting for the used equipment market. At the moment, everyone is tired of interesting times, and those in ... » read more

The Threat Within

By Connie Duncan Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called via... » read more

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