Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

Enabling Magnetic Tunnel Junctions Array Processing For Embedded STT MRAM


The semiconductor industry is entering a new era of next-generation memory technologies, with several major inflections taking shape. Among these is the emergence of Magnetic RAM (MRAM). Over several posts, I’ll provide background on what is driving the adoption of MRAM, highlight some of the initial challenges and discuss progress on making STT MRAM commerically viable. Today, a typical m... » read more

Electroplating IC Packages


The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Interconnect Challenges Rising


Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Back-End-of-Line (BEOL) Metallization


Physical Vapor Deposition (PVD) for Back-End-of-Line (BEOL) metallization is being pushed to the limits at the 16-nanometer (nm) technology node and beyond. Extending PVD for metal liner and barrier seed deposition is forcing the process into a narrow window that must be characterized prior to manufacturing introduction. Furthermore, understanding the liner dependency on the trench and via etch... » read more

The Trouble With MEMS


The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analo... » read more

Surprises At SEMICON West


As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about. Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that are driving growth and excitement at semiconductor equipment... » read more

Extending The Hardmask


In chip production, the backend-of-the-line (BEOL) is where the critical interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips. “The scaling roadblocks that the interconnect faces need to ... » read more

Will 7nm And 5nm Really Happen?


Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

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