The Importance Of Embedded In-Chip Monitoring In Advanced Node CMOS Technology


By Oliver King & Ramsay Allen With advances in CMOS technology and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased as has the process variability of devices manufactured. The increase in digital logic (or gate) density, which equates to an increase in power density, is a major contributor to... » read more

Mixed Messages For Mixed-Signal


There is no such thing as a purely digital design at advanced nodes today. Even designs that have no [getkc id="37" kc_name="analog"] content are likely relying on [getkc id="38" kc_name="mixed-signal"] components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single... » read more

Devices Threatened By Analog Content?


As the amount of analog content in connected devices explodes, ensuring that the analog portion works properly has taken on a new level of urgency. Analog circuitry is required for interpreting the physical world and for moving data to other parts of the system, while digital circuitry is the fastest way to process it. So a sensor that gives a faulty reading in a car moving at high speed or ... » read more

Closing The Power Integrity Gap


Voltage drop has always been a significant challenge. As far back as 130nm, specialist tools were being used to ensure that enough local decoupling capacitance (decap) cells were inserted in addition to larger decaps implemented around the SoC. But advanced nodes are complicating matters and further increasing complexity. These technological challenges, which underlie the power, performance ... » read more

Why Power Modeling Is So Difficult


Power modeling has been talked about for years and promoted by EDA vendors and chipmakers as an increasingly important tool for advanced designs. But unlike hardware and software modeling, which have been proven to speed time to market for multiple generations of silicon, power modeling has some unique problems that are more difficult to solve. Despite continued development in this field, po... » read more

IP Integration Challenges Increase


Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more