The Week In Review: Design


Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Blog Review: Nov. 15


Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

The Promises And Challenges Of 7nm


Despite a waning Moore’s Law and the increasing costs of advanced process nodes, the semiconductor industry is steadily approaching 7 nanometers (nm). The demand for 7nm is driving expected initial tape-outs from fabs by the end of 2017, with initial volumes beginning in 2018 and ramping up by 2019. Silicon fabbed on 7nm nodes will offer a number of benefits for chipmakers, including lower po... » read more

The Next Phase Of Machine Learning


Machine learning is all about doing complex calculations on huge volumes of data with increasing efficiency, and with a growing stockpile of success stories it has rapidly evolved from a rather obscure computer science concept into the go-to method for everything from facial recognition technology to autonomous cars. [getkc id="305" kc_name="Machine learning"] can apply to every corporate fu... » read more

Blog Review: Nov. 8


Synopsys' Eric Huang digs in to what's new with USB 3.2 and what's achieved by preserving the existing PHY signaling speeds. In a video, Mentor's Colin Walls provides tips on how to write debuggable and maintainable embedded code. Cadence's Paul McLellan listens in on a talk by Andrew Kahng of UC San Diego on the problem of scaling and why machine learning can improve EDA tools. Rambus... » read more

Automotive Cyber Security: From OTA Updates To Anti-Counterfeiting


The National Highway Traffic Administration (NHTSA) defines automotive cyber security as the protection of vehicular electronic systems, communication networks, control algorithms, software, users and underlying data from malicious attacks, damage, unauthorized access, or manipulation. From our perspective, automotive cyber security is one primary concern the industry must immediately addres... » read more

Security For Embedded Electronics


The embedded systems market is expected to enjoy steady growth in the near future—provided those systems can be adequately secured. One of the biggest challenges for embedded devices and systems, especially those employed in the [getkc id="76" comment="Internet of Things"], is adequately protecting them from increasingly sophisticated hacking. This is a new tool for criminal enterprises, a... » read more

Securing Smart Homes


One year after Mirai malware hijacked more than 100,000 connected devices for its botnet and launched a denial of service attack — which briefly blocked access to popular sites such as Netflix, PayPal, Amazon and Twitter — [getkc id="76" kc_name="IoT"] device makers are just beginning to get smarter about home security. Security concerns reach deeper into the home than just the Internet ... » read more

Cyber Security In The Era Of The Smart Home


The global smart home market is projected to reach at least $40 billion in value by 2020. Perhaps not surprisingly, OEMs are inadvertently creating major security risks in their rush to market by shipping smart home products with inadequate security and unpatched vulnerabilities. As ABI Research Analyst Dimitrios Pavlakis notes, ignoring cybersecurity at the design level provides a wide-open do... » read more

Blog Review: Nov. 1


Mentor's Nitin Bhagwath continues digging into DDR timing with a look at the clock-to-DQS requirement at the DRAM and how "write-leveling" is used to solve layout issues caused by the requirement. Synopsys' Dipesh Handa checks out what's new in the MIPI CSI-2 v2.0 specification that opens it up to new imaging and vision applications, including IoT and automotive. Cadence's Ken Willis delv... » read more

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