Doing More With RTL Power Analysis: Smart Synthesis Architecture


Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Low Power Design: RTL Power Analysis


In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

Bringing Electrical Info To Design’s Forefront


By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Wanted: ESL Power Design Flow


In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor. Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by w... » read more