Getting A Handle On RTL X-Verification Challenges


The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

Know What To Look For


With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Aren’t We Beyond That?


The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more