22nm Process War Begins


Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes. Seeking to satisfy a potential gap in the market, [getentity id="22819" comment="GlobalFoundries"], [getentity id="22846" e_name="... » read more

The Week In Review: Manufacturing


Fab tool vendors In the wafer fab equipment (WFE) rankings, Applied Materials was the leader in terms of market share in 2016, according to Gartner. For WFE, Lam Research jumped from fourth place in 2015 to second place in the rankings in 2016, according to Gartner. ASML was third, followed by TEL. Meanwhile, VLSI Research recently released its ranking for both front-end and backend equipment.... » read more

The Week In Review: Design


Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

The Other Side Of H1-B Visas


There is a lot of discussion these days about “Hire American.” But what does that actually mean in practice? I’m at the Materials Research Society Spring Meeting this week, where one of the presentations was by a scientist who works at the TEL Technology Center, America, in Albany, NY. It’s the largest Tokyo Electron research center outside of Japan. It’s affiliated with the SUNY P... » read more

The Week In Review: Design


M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

Time For Massively Parallel Testing


Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory devices and other semiconductors, test equipment vendors have resorted to parallel testing technology, simultaneously testing multiple chips at a time. The industry also is turning to system-level tes... » read more

Pushing Batteries Too Far?


Reports of battery fires in consumer devices are not abating. The culprit in almost all cases is the lithium-ion battery. In some cases, this is a manufacturing issue, where predictable intervals of failure can point to a breach in the membrane separating the anode and cathode or a metal particle contaminant that causes a short circuit. Those kinds of flaws are well understood, based upon ho... » read more

The Week In Review: Manufacturing


Chipmakers At an event, Intel’s Technology and Manufacturing group outlined the company's vision. As part of the event, Intel reiterated what many are saying—the current node designations are meaningless and misleading. “For example, Intel estimates that its 14nm solution that has been out in the market since 2014 should be equal to 10nm solutions released by competitors in the near futu... » read more

The Week In Review: Manufacturing


Chipmakers China’s IC industry is embarking on a recruitment drive to prepare for the operation of new fabs in 2018, according to TrendForce. “TrendForce’s latest analysis on China’s semiconductor sector reveals that the country’s domestic IC manufacturers are affecting the movement of industry talent worldwide as they continue to aggressively headhunt for senior managers and enginee... » read more

The Week In Review: Design


Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

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