Too Big To Simulate?


With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

Emulation’s Footprint Grows


It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

Why I See C In SCE-MI


The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Predictions For 2016: Tools and Flows


Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Say Hi To Hybrid


It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

UVM: What’s Stopping You?


These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Continuous, Connected And Concurrent Verification


By Ed Sperling It’s a wonder that any electronic system works as intended, or that it continues to work months or years after it is sold. The reason: SoCs have become so complex that no verification coverage model is sufficient anymore, no methodology covers every aspect of verification, and no single tool or even collection of tools can catch every bug or prevent them from being there in th... » read more