tag: Security Verification

Verifying Hardware Security With RTL Simulation
By Taruna Reddy - 14 Mar, 2024 - Comments: 0

When consumers think about security for their electronic gadgets, financial applications probably spring first to mind. Identity theft and unauthorized access to bank and investment accounts are a constant threat. But there’s more to worry about every day. Stories of webcams and smart speakers being hacked are all over the web. Users rightfully demand that device manufacturers provide a high ... » read more

Creating Comprehensive And Verifiable Hardware Security Requirements
By Anders Nordstrom - 01 Dec, 2022 - Comments: 0

Developing effective hardware security requirements is one of the trickiest aspects of building trustworthy electronic products. Even highly skilled and experienced teams don’t always get it right. Why? First, it’s very difficult to anticipate every security risk – much less cover every possible scenario with a specific security requirement. Instead, hardware security requirements o... » read more

Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program.   The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

Ensuring Security By Design Is Actually Secure
By Melissa Jordan - 05 May, 2022 - Comments: 0

Today’s connected systems touch nearly every part of consumers’ lives, from smart thermostats in our homes to self-driving cars on our roads. The adoption of these new devices has led to an explosion of new semiconductors and use models. But these novel conveniences also come with new risks. With vulnerabilities on the rise and the potential for remote attacks growing, product companies mus... » read more

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions
By Technical Paper Link - 28 Mar, 2022 - Comments: 0

Abstract "The ever-increasing usage and application of system-on-chips (SoCs) has resulted in the tremendous modernization of these architectures. For a modern SoC design, with the inclusion of numerous complex and heterogeneous intellectual properties (IPs),and its privacy-preserving declaration, there exists a wide variety of highly sensitive assets. These assets must be protected from any u... » read more

Security Verification For Processor-Based SoCs
By Ruud Derwig - 02 Apr, 2020 - Comments: 0

By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. End-product system security, however, cannot be guaranteed by using a secure processor alone. The final product security results not only from using proven, secure hardware component... » read more

Verifying Security In Processor-based SoCs
By Ruud Derwig - 12 Dec, 2019 - Comments: 0

By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

OneSpin Users Gather in Munich
By Rob van Blommestein - 02 Dec, 2019 - Comments: 0

Even more than most other high-tech companies, EDA vendors rely on their users for many aspects of their success. Of course, customers provide the revenue that fuels the business, but their influence goes far beyond that. Many features in EDA tools, and even entire categories of products, arise from working closely with advanced users. Even before traditional Beta-testing, selected users provid... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Verifying Security Aspects of SoC Designs with Jasper App
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

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