Examining DevSecOps Realities And Opportunities


We are still in the early days of including security in continuous integration (CI), continuous delivery (CD), and DevOps workflows. Given that only half of enterprise deployments include security testing elements today, there’s still plenty of room for improvement. Enterprises implementing CI, CD, and DevOps releases are working with large-scale infrastructures, focusing on faster release... » read more

Designing Hardware For Security


By Ed Sperling and Kevin Fogarty Cyber criminals are beginning to target weaknesses in hardware to take control of devices, rather than using the hardware as a stepping stone to access to the software. This shift underscores a significant increase in the sophistication of the attackers, as evidenced by the discovery of Spectre and Meltdown by Google Project Zero in 2017 (made public in Ja... » read more

The Week In Review: Design


M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

Improving Security In Cars


When security researchers first demonstrated that they could hack a car over the internet to control its brakes and transmission, Chrysler had to recall 1.4 million vehicles to fix the software vulnerability. The infamous Jeep hack of 2015 was an expensive wake-up call for the automotive industry. So, what has changed since then? In today’s cars, software now controls everything from safet... » read more

Tech Talk: HW Security


Ben Levine, senior director of product management at Rambus, explains how to minimize the risk of attacks on chip hardware, why design for security is becoming more critical for connected devices, and strategies for making devices less vulnerable. https://youtu.be/twgHcdqvyjU » read more

Cache Speculation Side-Channels


Cache timing side-channels are a well understood concept in the area of security research. As such, this whitepaper will provide a simple conceptual overview rather than an in-depth explanation. The basic principle behind cache timing side-channels is that the pattern of allocations into the cache, and, in particular, which cache sets have been used for the allocation, can be determined by m... » read more

Connected Car Driving Defect Detection Change


Automotive product design is rapidly evolving and the magnitude and pace of change facing engineering organizations is challenging incumbent processes and resources, especially in the area of software design. While connected cars are not new, the frequency and depth to which the industry is embracing this dynamic is accelerating. Software has emerged as a primary vehicle for innovation and diff... » read more

Hidden Costs Of Shifting Left


The term "Shift Left" has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks. One such example being talked about today is the need to perform hardware/software integration much earlier in the flow, rather than leaving it as a sequ... » read more

New Market Drivers


Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohammed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techn... » read more

Blog Review: Apr. 25


Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

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