Timing Closure Issues Resurface


Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

Fill/Cut Self-Aligned Double-Patterning


By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke Self-aligned double patterning (SADP) is an alternative double-patterning process to the traditional litho-etch-litho-etch (LELE) approach used in most advanced production nodes. The main difference between the two approaches is that in LELE, the layout is divided between two masks, and the second mask is aligned with resp... » read more

1xnm DRAM Challenges


At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Flash Dance For Inspection And Metrology


Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

Self-Aligned Double Patterning—Part Deux


In my last article, I introduced you to the basic Self-Aligned Double-Patterning (SADP) process that is one of the potential candidate techniques for processing metal layers at 10nm and below, but let’s have a quick recap. SADP uses a deposition and etch step process to create spacers surrounding a patterned shape (Figure 1). As you can see, there are two masking steps—the first mask is cal... » read more

Self-Aligned Double Patterning, Part One


I’m sure most of you have seen a Rorschach test ink blot (Figure 1). Psychiatrists ask the subjects to tell them what they “see” in the ink blot. The answers are used to characterize the respondent’s personality and emotional functioning. I am never sure if I would feel more uncertain being the psychiatrist asking the question, or the subject trying to decide what to say, given there ar... » read more

What If EUV Fails?


It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

One-on-One: Naoya Hayashi


Semiconductor Engineering sat down to discuss the current and future challenges in the photomask industry with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). SE: What are the big challenges for the photomask industry today? Hayashi: There are several challenges. Most of the challenges involve mask complexity. It is also quite difficult to handle the mask data, because it is ... » read more