Bringing Electrical Info To Design’s Forefront


By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Good Pattern Flow Ahead For 14, 10nm


By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Are There Enough Cooks In The Kitchen?


We work in a fascinating industry, without a doubt, and I watch with interest to see the new technologies that the industry decides to adopt. finFETs and FD-SOI are some really cool technologies, in particular, with great promises. You might also know that we follow innovations in the world of chip design and manufacturing every week from academia and research institutes on all of our communiti... » read more