U.S. Strategy on Microelectronics Research


The U.S. government released a 61 page report titled "National Strategy on Microelectronics Research" by the Subcommittee On Microelectronics Leadership, Committee on Homeland and National Security of the National Science and Technology Council. The report states four goals guiding the agency's efforts in microelectronics research: "Goal 1. Enable and accelerate research advances for futu... » read more

Industry 4.0 Paradigms For Chip Workforce Development And Domestic Production: Using Automation And AR/VR


A technical paper titled “From Talent Shortage to Workforce Excellence in the CHIPS Act Era: Harnessing Industry 4.0 Paradigms for a Sustainable Future in Domestic Chip Production” was published by researchers at University of Florida Gainesville, ZEISS Microscopy, and US Partnership for Assured Electronics (USPAE). Abstract: "The CHIPS Act is driving the U.S. towards a self-sustainable f... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology


A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Collaboration Widens Among Big Chip Companies


Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computati... » read more

New Data Management Challenges


An explosion in semiconductor design and manufacturing data, and the expanding use of chips in safety-critical and mission-critical applications, is prompting chipmakers to collect and manage that data more effectively in order to improve overall performance and reliability. This collection of data reveals a number of challenges with no simple solutions. Data may be siloed and inconsistent, ... » read more

CHIPS Act: U.S. Releases New Implementation Strategy


The U.S. Department of Commerce today published "A Strategy For The CHIPS For America Fund," outlining its implementation approach to distributing $50 billion from the CHIPS Act of 2022. Find the full strategy paper here, and the executive summary here. Program Goals The program's four primary goals are: Establish and expand domestic production of leading edge semiconductors in ... » read more

Cubic Boron Arsenide’s Unique Semiconducting Properties (MIT)


New research claims cubic boron arsenide could be a “game-changing” semiconductor with a “very high mobility for both electrons and holes,” according to this MIT article. “Heat is now a major bottleneck for many electronics,” says Shin, the paper’s lead author. “Silicon carbide is replacing silicon for power electronics in major EV industries including Tesla, since it has thr... » read more

Week in Review: Manufacturing, Test


Fab capacity STMicroelectronics and GlobalFoundries inked a deal to build a new jointly-operated 300mm fab adjacent to ST’s existing 300mm facility in Crolles, France. This facility is targeted to ramp at full capacity by 2026, with up to 620,000 300mm wafer per year production at full build-out (~42% ST and ~58% GF). The new facility will support several technologies, with a special focus... » read more

Customization, Heterogenous Integration, And Brute Force Verification


Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

What Future Processors Will Look Like


Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

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