Respecting Reset


Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

Huawei Delivers Outstandingly Accurate Models


By John Parry, Mentor, a Siemens Business, and Yake Fang, Huawei Technologies Co., Ltd. Packaging high-performance multi-core IC devices used in communication applications is a key challenge for both manufacturers and system integrators. Traditionally a System-in-Package (SiP) has been taken, with chips mounted side-by-side, allowing differing semiconductor technologies to be mixed. More r... » read more

Toward Continuous HW-SW Integration


Hardware is only as good as the software that runs on it, and as system complexity grows that software is lagging behind. The way to close that gap is to improve the [getkc id="100" kc_name="methodology"] for developing that software in the first place. That includes making sure updates are verified and tested before being pushed out to devices, adding the same kinds of detailed checks that ... » read more

Verification Unification


There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Whatever Happened To HLS?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

Blog Review: May 24


Mentor's Andrew Patterson questions who should have control over who sees the vast amounts of data generated by automobiles and how it is used. In a series of posts, Cadence's Meera Collier considers philosophical questions from the angle of computer science. Synopsys' Eric Huang has a lighthearted look at today's world of robots. Rambus' Aharon Etengoff points to Director of National ... » read more

Maintaining Power Profiles At 10/7nm


Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Blog Review: May 17


Synopsys' Robert Vamosi digs into last Friday's massive ransomware infection that impacted the UK health system, a Spanish telecom, and many other organizations running unpatched Windows – and whether there's a second version out there. Cadence's Paul McLellan reports on the latest developments and future of FD-SOI from the SOI Silicon Valley Symposium. Mentor's Joe Hupcey III chats wit... » read more

Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Moore’s Law: Toward SW-Defined Hardware


Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

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