tag: signoff

A Shift Left Strategy Is One Part Of A Holistic Approach To IC Design Verification
By David Abercrombie - 28 Sep, 2023 - Comments: 0

The whole is more than the sum of its parts. –Aristotle A machine is nothing more than a collection of nuts, bolts, wheels, gears, wires, pipes, chains, and what have you. And yet, when they are all connected up properly, magic happens. Instead of a pile of parts, you have a car, or a dishwasher, or a nuclear reactor. The connections and interactions between all those parts turns the whole... » read more

Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster
By Kesmat Shahin - 23 Feb, 2023 - Comments: 0

Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule ... » read more

Tempus Timing Signoff Solution
By Cadence - 23 Nov, 2022 - Comments: 0

The Cadence Tempus Timing Signoff Solution is the fastest static timing analysis (STA) tool in the industry today with unique distributed processing and cloud capabilities enabling hundreds of CPUs to quickly complete even the largest designs. With full foundry certification and a comprehensive set of advanced capabilities, the Tempus solution delivers SPICE-accurate results to hundreds... » read more

Golden Signoff ECO For Last-Mile Electronic Design Closure
By Manoj Chacko - 03 Oct, 2022 - Comments: 0

Electronic design developers really hate iterative, resource-intensive tasks that occur late in the project schedule. Most engineers are under tremendous time to market (TTM) pressure due to competition while being told that they must minimize the cost of both the project and the end chip. In addition, they are struggling to meet power, performance, and area (PPA) requirements far more aggressi... » read more

Verification Signoff Beyond Coverage
By Paul Graykowski - 03 Feb, 2022 - Comments: 0

A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. Th... » read more

In-Design Signoff DRC For Productivity Improvement
By Srinivas Velivala - 26 Aug, 2021 - Comments: 0

Microsemi, a wholly-owned subsidiary of Microchip Technology, produces a portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. In addition to high-performance and radiation-hardened analog/mixed-signal integrated circuits, FPGAs, SoCs and ASICs, they also design power management products, timing and synchronization devices, ... » read more

Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow
By Synopsys - 06 Jul, 2021 - Comments: 0

For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

Precision: A Case Study For Success
By Rob van Blommestein - 09 Jun, 2021 - Comments: 0

Recently, I was watching a documentary on the NASA Perseverance mission to Mars. I’ve always been fascinated by space travel and the engineering efforts to make it happen. We’ve all heard that the landing for this trip to Mars was the most precise in history, but what the documentary brought to light is the precision involved in each and every aspect of the Perseverance Rover design and dev... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Electro-Thermal Signoff For Next Gen 3DICs
By Ansys - 09 Sep, 2020 - Comments: 0

Multi-die designs, 2.5D and 3D, have been rising in popularity as they offer tremendously increased levels of integration, a smaller footprint, performance gains and more. While they are attractive for many applications, they also create design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterpa... » read more

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