tag: Silicon Labs

Blog Review: March 17
By Jesse Allen - 17 Mar, 2021 - Comments: 0

Synopsys' Chris Clark considers the growing number of automotive sensors and the cost/performance tradeoffs between edge computing capability, sensor fusion, sensor degradation, monitoring, and the maintenance of the software over the lifespan of a vehicle. Cadence's Paul McLellan checks out how the process of loading the bootstrap into memory has changed over the years, from hand-entered on... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 12 Feb, 2021 - Comments: 0

Automotive/Mobility With the chip supply so tight it is shutting down automotive production lines, U.S. chip company CEOs signed a Semiconductor Industry Association (SIA) letter asking the U.S. president to include funding incentives for the chip manufacturing in U.S. economic recovery plans. The letter references the CHIPS for America Act and asks the president to work with Congress to suppo... » read more

RISC-V Becoming Less Risky With The Right Verification
By Rob van Blommestein - 25 Jan, 2021 - Comments: 1

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the ... » read more

Blog Review: Dec. 23
By Jesse Allen - 23 Dec, 2020 - Comments: 0

Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

RISC-V Verification Challenges Spread
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

Blog Review: Nov. 25
By Jesse Allen - 25 Nov, 2020 - Comments: 0

Mentor's Harry Foster finds growing complexity in FPGA design by looking at the number of embedded microprocessors, asynchronous clock domains, and safety/security features in the 2020 Wilson Research Group Functional Verification Study. Cadence's Paul McLellan points to the interim SRC/SIA Decadal Plan for Semiconductors and five big shifts it identifies in information and communication tec... » read more

Blog Review: Nov. 11
By Jesse Allen - 11 Nov, 2020 - Comments: 0

Mentor's Chris Spear proposes mixing together the compactness of the field macro style with the preciseness of the do methods when writing a UVM transaction class. Cadence's Paul McLellan looks back at the history of EPROM, some of the difficulty with actually erasing it, and the subsequent development of EEPROM. Synopsys' Tuomo Untinen explains three WPA2 authentication vulnerabilities r... » read more

Blog Review: June 24
By Jesse Allen - 24 Jun, 2020 - Comments: 0

Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

What Makes A Chip Tamper-Proof?
By Bryon Moyer - 04 Jun, 2020 - Comments: 5

The cyber world is the next major battlefield, and attackers are busily looking for ways to disrupt critical infrastructure. There is widespread proof this is happening. “Twenty-six percent of the U.S. power grid was found to be hosting Trojans," said Haydn Povey, IAR Systems' general manager of embedded security solutions. "In a cyber-warfare situation, that's the first thing that would b... » read more

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