The Next 5 Years Of Chip Technology

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

Application Of Richardson Extrapolation To The Co-Simulation Of FMUs From Building Simulation

The application of the FMI technology gains ground in building simulation. As far as specialized tools support the FMI simulator coupling becomes an important option to simulate complex building models. Co-simulation needs a master algorithm which controls the communication time steps as well as the signal exchange between FMUs. Often a constant communication step size is applied chosen by the ... » read more

Why EDA Needs To Change

Why is it taking so long for [getkc id="305" kc_name="machine learning"] to have an impact within EDA? Most of the time when I talk to the experts within the field I hear about why designs are so different from other machine learning applications, and I know that is true. Many of you reading this may not be aware that I was a developer of EDA tools for more than 35 years before I ended up writi... » read more

Tech Talk: Applying Machine Learning

Norman Chang, chief technologist at ANSYS, talks about real applications of machine learning for mechanical, fluid dynamics and chip-package-system design. » read more

Artifacts Of Custom Checkers In Questa Power-Aware Dynamic Simulation

UPF provides a powerful mechanism to define a custom PA checker or assertion and provides a layer to completely separate it from design code. This is done by embedding the binding of the design and checker within the UPF file through the bind_checker command and its options. As a result, it provides a consolidated verification mechanism and allows Questa PA-SIM to access all instances of a targ... » read more

What’s In The Package?

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

System-Level Simulation Of Technologies Supporting Enhanced Spectral Efficiency For 5G New Radio

By Gent Paparisto, Joel Kirshman, and David Vye 5G New Radio (5G NR) is the wireless standard defining the next generation of mobile networks. 5G will offer higher capacity than current 4G, enabling a higher density of mobile broadband users and supporting device-to-device and massive-machine communications. 5G research and development will support lower latency, improved reliability, and... » read more

The Week In Review: Design

Startups Two new companies unveiled this week – Metrics Technologies and Movellus. Metrics Technologies is providing a Software-as-a-Service SystemVerilog simulator and verification manager that are available as pay-per-minute. This allows companies to have fully elastic system capabilities to accommodate peak simulation demand. “Cloud technology and Software as a Service business mo... » read more

Achieving RTL-To-Netlist Equivalence

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

Reflection On 2017: Design And EDA

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

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