tag: statistical timing

Experts At The Table: Challenges At 20nm

By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Trending Articles

Silicon Photonics Manufacturing Ramps Up

The promise of photonics ICs is spurring innovation, but complex processes and a lack of open foundries are keeping it from reaching its full potential.

by Gregory Haley

Chip Industry Week In Review

Applied Materials' $4B facility at risk; AI chip bonanza; Japan, U.S. alliance; Rapidus' U.S. subsidiary; EDA revenue up; TSMC $6.6B funding; Infineon, Amkor team up; S. Korea's big bet; Apple's processor overhaul; high-NA EUVL defect system; chiplet HW security module; new Spectre attack.

by The SE Staff

Chip Industry Week In Review

China restricts U.S. processors; Samsung's CXL, DRAM module and roadmap; ASML's $2.7B retention bonus; U.S., Mexico partner up; Keysight's $1.5B offer to Spirent; Lam's new pulsed laser deposition; new OSAT center.

by The SE Staff

Digital Twins Target IC Tool And Fab Efficiency

Virtual representations will improve performance and productivity across the entire design through manufacturing flow, but deployments will vary in effectiveness and timelines.

by Laura Peters

Early STEM Education Key To Growing Future Chip Workforce

Community outreach and partnerships can drive interest in STEM subjects and chip jobs among children, parents, and teachers.

Knowledge Centers
Entities, people and technologies explored

Related Articles

The Rising Price Of Power In Chips

More data requires faster processing, which leads to a whole bunch of problems — not all of which are obvious or even solvable.

by Ed Sperling

The Future Of Memory

From attempts to resolve thermal and power issues to the roles of CXL and UCIe, the future holds a number of opportunities for memory.

by Karen Heyman

SRAM Scaling Issues, And What Comes Next

While it will remain a workhorse memory, using SRAM at advanced nodes requires new approaches.

by Karen Heyman

Verifying Hardware Security With RTL Simulation

Measuring how injected faults propagate through a design and how long they remain in the system.

by Taruna Reddy

Backside Power Delivery Adds New Thermal Concerns

Lack of shielding, routing issues, and new mechanical stresses could have broad impact on standard cell design.

by Karen Heyman

Glitch Power Issues Grow At Advanced Nodes

Problem is particularly acute in AI accelerators, and fixes require some complex tradeoffs.

by Ann Mutschler

Rethinking Memory

Von Neumann architecture is here to stay, but AI novel architectures and 3D structures create a need for new testing tools.

by Karen Heyman

SRAM’s Role In Emerging Memories

Tools and optimizations are needed for SRAM to play a role in AI hardware; other memories make inroads.

by Karen Heyman

About

Navigation

Connect With Us

Facebook
Twitter @semiEngineering
LinkedIn
YouTube

Copyright ©2013-2024 SMG | Terms of Service | Privacy Policy