Moore’s Law: A Status Report


Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Board Level Reliability Of Automotive Embedded Wafer-Level BGA FOWLP


With shrinking chip sizes, Wafer Level Packaging (WLP) is becoming an attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out Wafer Level Packaging (FOWLP) designs, this advanced technology has proven to be a more optimal and promising solution compared to fan-in WLP because of the greater design flex... » read more

2.5D, FO-WLP Issues Come Into Focus


Advanced packaging is beginning to take off after years of hype, spurred by 2.5D implementations in high-performance markets and fan-out wafer-level packaging for a wide array of applications. There are now more players viewing packaging as another frontier driving innovation. But perhaps a more telling sign is that large foundries in Taiwan have begun offering packaging services to customer... » read more

How Testing MEMS, Sensors Is Different


When it comes to testing microelectromechanical system devices and sensors, sometimes you have to shake and bake. [getkc id="311" comment="MEMS"] and [getkc id="187" kc_name="sensors"] are physically different from standard ICs. They require a specific type of stimulus to get the required testing results. Most chips only need to have an electrical charge run through them to gauge their pass/... » read more

Electroplating IC Packages


The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

The Week In Review: Manufacturing


Chipmakers At this week’s TSMC Technology Symposium in San Jose, Calif., TSMC rolled out a dizzying array of new processes and technologies. Perhaps the most surprising announcement was a 22nm bulk CMOS process, which is geared for ultra low-power planar chips. The technology will compete against a 22nm FD-SOI technology from GlobalFoundries. Stay tuned. The battle has just begun. As e... » read more

MEMS: Improving Cost And Yield


MEMS devices inspire awe on the design side. On the test and manufacturing side, they evoke a different kind of reaction. These are, after all, the intersection of mechanical and electrical engineering—a joining of two miniature worlds that are the basis of some of the most complex technology on the planet. But getting these devices to yield sufficiently, understanding what does or does no... » read more

Advanced Wafer Level Packaging Of RF-MEMS With RDL Inductor


The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in ... » read more

2.5D Adds Test Challenges


OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

Crossing The Chasm: Uniting SoC And Package Verification


Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

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