The Week In Review: Manufacturing


Trade The trade tensions are building between the U.S. and China. In the latest move, the U.S. Department of Commerce has imposed a ban on U.S. companies selling chips to ZTE, a Chinese telecom equipment and mobile phone vendor. The ban has been implemented on ZTE for seven years after the firm “was caught illegally shipping U.S. goods to Iran,” according to a report from Reuters. This... » read more

Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology


Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effective... » read more

Fan-Out Wars Begin


Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Cheaper Packaging Options Ahead


Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution


System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

The Week In Review: Manufacturing


Market research The SEMI Industry Strategy Symposium (ISS) opened with the theme “Smart, Intuitive & Connected: Semiconductor Devices Transforming the World.” Click here for some of the highlights at ISS. Here are more highlights from ISS. Korea is on a spending spree for fab tools. In total, Samsung and SK Hynix are forecast to invest over $20 billion in fab tools worldwide in 2018, ... » read more

Packaging Challenges For 2018


The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution


System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Fan-Outs vs. TSVs


Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications


With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

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