The Problem With Clocks


The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

Managing Voltage Drop At 10/7nm


Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

10nm And 7nm Routability – How Is Your CAD Flow Doing?


At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs - Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting fee... » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

Worst-Case Results Causing Problems


The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to create its own set of issues. This is particularly true at 16/14nm and below, where extra circuitry can slow performance, boost the amount of power required to drive signals over longer, thinne... » read more

What Can Be Cut From A Design?


A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Routing Signals At 7nm


[getperson id="11763" comment="Tobias Bjerregaard"], [getentity id="22908" e_name="Teklatech's"] CEO, discusses the challenges of designs at 7nm and beyond, including power integrity, how to reduce IR drop and timing issues, and how to improve the economics of scaling. SE: How much further can device scaling go? Bjerregaard: The way you should look at this is [getkc id="74" comment="Moore... » read more

Mobile Processors Move Beyond Phones


Mobile processors, also known as application processors, are well-known as the engines that run smartphones, tablet computers, and other wireless devices. But these chips increasingly are finding their way into autonomous vehicles, the Internet of Things, unmanned aerial vehicles, virtual reality, and other applications far beyond phone calls and text messages. Moreover, they are gaining in com... » read more

Dynamic Peak Power As A Proxy For DVD? Really?


Dynamic-voltage-drop (DVD) concerns have grown substantially at the 10nm and 7nm silicon process nodes. DVD refers to the transient voltage drop that a local power grid on a chip might experience if there is a rapid change in current. That drop can act like a “stall,” hurting performance until the grid recovers. Beefing up the power grid metal might seem to be the obvious fix, but, at th... » read more

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