Hierarchical Timing Analysis: Pros, Cons, And A New Approach

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain blocks of logic, generating results more quickly and with fewer memory resources. However, these benefits come at the cost of accuracy. This paper covers the pros and cons of different hierarchica... » read more

Timing Bomb

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more