How To Reduce Timing Closure Headaches

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

Tear Down The Wall Between Front-End And Back-End Teams

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

Constraints Ubiquity: Impact On Managing Design Closure?

By Mark Baker and Ravindra Aneja Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration ... » read more

Timing Bomb

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more