The Week In Review: Design


M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

Regain Your Power With Machine Learning


It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

How To Close Timing With An eFPGA Hosted In An SoC


eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more

Tech Talk: 7nm Power


Annapoorna Krishnaswamy, lead applications engineer at ANSYS, talks with Semiconductor Engineering about power-related changes at 7nm and what engineering teams need to watch out for as they move down to the latest process technology. https://youtu.be/Ym46ssJPeHM » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis


As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below


At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

The Secret To Good Comedy And SystemC Code Verification… Timing!


The High-Level Synthesis (HLS) of algorithmic code, usually written in SystemC, is steadily gaining ground. However, the verification of this code is still a somewhat mixed-up, ad-hoc process. The situation is improving as new techniques are applied, but it is clear that in-the-trenches evaluation of these solutions on real projects is more important right now than grand visions missing substan... » read more

Tech Talk: 14nm


Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

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