Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below


At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

The Secret To Good Comedy And SystemC Code Verification… Timing!


The High-Level Synthesis (HLS) of algorithmic code, usually written in SystemC, is steadily gaining ground. However, the verification of this code is still a somewhat mixed-up, ad-hoc process. The situation is improving as new techniques are applied, but it is clear that in-the-trenches evaluation of these solutions on real projects is more important right now than grand visions missing substan... » read more

Tech Talk: 14nm


Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

The Interconnected Web Of Power


Tradeoffs between area and timing used to follow fairly simple rules. You could improve timing by adding area, and occasionally find an architectural solution that would decrease both at the same time. With physical synthesis the relationship became a little more complicated because an increase in area, say to make a drive larger or add another buffer, might upset the layout. That, in turn, cou... » read more

Plunify: FPGA Design Closure


The number of EDA startups has plummeted around the globe, and nowhere is this more evident than in Singapore. In fact, there is exactly one EDA startup in that country—[getentity id="22672" e_name="Plunify"]—and even that isn't so new. Plunify started life in 2009 as a cloud-based startup, whose mission was to provide public cloud compute services to companies developing FPGAs. While th... » read more

First Look: 10nm


As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

Avoiding Pitfalls While Specifying Timing Exceptions


Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where timing is either not relevant (e.g., set_false_path command in SDC) or can be relaxed (e.g., set_multicycle_path command in SDC), instructing static timing analysis (STA) and implementation tools to... » read more

The X Factor


By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

Rethinking Timing Optimization


By Ann Steffora Mutschler As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node. “With lower nodes we are getting advantage on area, more and more logic is get... » read more