tag: TLM-2.0

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Taking Stock Of Models
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler The world of modeling in SoC design is multi-dimensional to say the least. One dimension contains the model creators and providers, while the other is comprised of the types of models that exist in the marketplace. “What we’re seeing today is that we have basically models coming from either IP providers—the people that are actually producing those cores ... » read more

The Fine Art Of Compromise
By Jon McDonald - 19 Dec, 2012 - Comments: 0

By Jon McDonald Ask 10 people a question and you might get 10 different answers. Ask 10 software engineers what they need in a hardware platform and you might get more than 10 different answers because each probably will have a list of needs for the platform to deliver. Getting them to agree on acceptable targets may not be as difficult as a budget compromise, but project failure is a more pe... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

Being Different Is Bad
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Today’s SoCs contain as much as 80% existing IP that either has been re-used from previous projects or obtained from a third party. Models are created of this hardware IP, as well as new portions of the design, in order to create a virtual prototype that allows the engineering team to see the complete system by running software and applications. While this a... » read more

Designing In The Rain
By Jon McDonald - 23 Aug, 2012 - Comments: 0

By Jon McDonald Recently I was running some errands on my motorcycle when I got caught in the rain. Living in Florida, this is a fairly common summer occurrence. Generally, as long as it’s not too much of a deluge, I can continue through to my destination and dry off when I arrive. I always get concerned looks from those going by in their enclosed vehicles—from some, “concerned” mig... » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

The Trouble With Models
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Models and modeling concepts seem to be on the tip of every tongue these days. Once the promise of sparking true ESL design, the use of system-level models has settled into something more like enabling software development. There is also talk of leveraging models across the supply chain, but is this really possible yet? The concept of doing this incremental refinem... » read more

Model-Driven Design: Making Progress
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Model-driven design is coming into its own, in part because the old way of using models at advanced nodes doesn’t always produce usable chips and in part because of the need for making tradeoffs at the earliest stages of the design process. The concept of developing models for IC design is hardly a new one, and it is being done today on a number of levels rangin... » read more

Standards Update
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

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