Emulation’s Footprint Grows

It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

What’s Next For UVM?

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

System-Level Verification Tackles New Role

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

Outlook 2016 – The year of Horizontal and Vertical Flow Integration

As 2015 comes to an end rapidly, the key question becomes what the next year will bring. Last year around this time, in my blog “The Next Big Shift In Verification”, I talked about software-driven verification as the next era of verification that follows the eras of directed testing and High-level Verification Language (HVL) driven verification. I also had referred to our System Development... » read more

Say Hi To Hybrid

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

Simulation Performance Driven By Model Efficiency

In real estate it’s all about location, location, location. For system level simulation it’s all about performance, performance, performance. I have heard many opinions on the performance of SystemC and TLM simulations: some positive, some negative, much of the opinion based on hearsay or other unreliable information. I believe the performance of the simulation is mainly driven by the model... » read more

Important Changes Ahead

Two of Si2's important industry standards efforts will be featured later this month at DesignCon, a popular Silicon Valley event that is now in its 20th year. In the panel entitled, "System-Level Power Modeling—What's the Big Deal?", leading industry experts from AMD, Avago Technologies, Cadence, Docea Power, Qualcomm, and Si2 will focus on the growing need to take a higher level and more... » read more

Vista Virtual Prototyping

Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with board support packages, providing sufficiently fast simulation models for OS and application software validation. The Vista Virtual Prototyping solution has two dist... » read more

What’s Ahead For System-Level Design

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

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