Four Foundries Back MRAM


Four major foundries plan to offer MRAM as an embedded memory solution by this year or next, setting the stage for what finally could prove to be a game-changer for this next-generation memory technology. GlobalFoundries, Samsung, TSMC and UMC plan to start offering spin-transfer torque magnetoresistive RAM (ST-MRAM or STT-MRAM) as an alternative or a replacement to NOR flash, possibly start... » read more

Why Fabs Worry About Tool Parts


Achieving high yields with acceptable costs is becoming much more difficult as chipmakers migrate to next-generation 3D NAND and finFET devices—but not just because of rising complexity or lithography issues. To fabricate an advanced logic chip, for example, a wafer moves from one piece of equipment to another in what amounts to 1,000 process steps or more in a fab. Any glitch with the equ... » read more

The Week In Review: Manufacturing


Fab tools Lam Research held an analyst event this week. The company indicated that the industry is in the midst of a memory boom, including both DRAM and 3D NAND. According to Amit Daryanani, an analyst with RBC, here was one of the big takeaways at the event: “The memory spend portion of WFE is more sustainable than previously assumed due to end-market drivers such as big data, automation, ... » read more

Electroplating IC Packages


The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Patterning Problems Pile Up


Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

BEOL Issues At 10nm And 7nm


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

BEOL Issues At 10nm And 7nm


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Etching Technology Advances


Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

BEOL Issues At 10nm And 7nm


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

BEOL Barricades Ahead


Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. Among the questions posed to panelists: What is BEOL? Where does it begin and end? Are there fundamental limits to interconnect processes? How much longer can we continue to use current interconnect processes and te... » read more

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