TSVs: Copper, Silicon, And CTE Mismatch


As previous articles in this series have discussed, advanced packages introduce new materials and new reliability concerns. Diffusion into solder bumps can create brittle, high resistance, intermetallic compounds. Heat transfer through an interposer can degrade the lifetime of even cool, low power chips. Still, through-silicon vias are unique in that they cut directly through the integrated cir... » read more

Advanced Packaging Options, Issues


Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features. Cost has been one of the big deterrents for widespread adoption of [getkc id="82" kc_name="2.5D"]. Initially, the almost universal compla... » read more

One-On-One: Dave Hemker


Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

Keeping The Whole Package Cool


Heat dissipation is a critical issue for designers of complex chip-stacking and system-in-package devices. The amount of heat generated by a device increases as the number of transistors goes up, but the ability to dissipate the heat depends on the package surface area. Because the goal of 3D packaging is to squeeze more transistors into less overall space, new heat dissipation issues are em... » read more

2.5D Becomes A Reality


Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

High-Bandwidth Memory


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

New Memory Approaches And Issues


New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

Tech Talk: 2.5D Issues


Bill Isaacson, director of ASIC marketing at eSilicon, about how viable this packaging approach is, organic vs. inorganic interposers, where the problems are, thermal coupling, interposer cost, and what will change over the next couple years. [youtube vid=t6KUnC-oU5g] » read more

What’s Next For DRAM?


The DRAM business has always been challenging. Over the years, DRAM suppliers have experienced a number of boom and bust cycles in a competitive landscape. But now, the industry faces a cloudy, if not an uncertain, future. On one front, for example, [getkc id="93" kc_name="DRAM"] vendors face a downturn amid a capacity glut and falling product prices in 2016. But despite the business chal... » read more

Will 3D-IC Work?


Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

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