Can Verification Meet In The Middle?

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Debug: Last Bastion Of Automation

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

ROI Not There Yet For SysML

At some point down the road in the realm of system-level design, the Systems Modeling Language (SysML) dialect of the Unified Modeling Language (UML) standard may drive into semiconductor design. So far, however, a return on investment has not been established for its use. SysML is defined as a general-purpose visual modeling language for systems engineering applications, and it supports the... » read more

The Next Level Of Abstraction For System Design

Recently there have been a lot of discussions again about the next level of design abstraction for chip design. Are we there yet? Will we ever get there? Is it SystemC? UML/SysML perhaps? I am taking the approach of simply claiming victory: Over the last 20 years we have moved up beyond RTL in various areas—just in a fragmented way. However, the human limitations on our capacity for processin... » read more

More Data, Different Approaches

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

Top-Down SoC Verification

In the world of system-on-chip (SoC) verification, 2014 was an interesting year of transition. After much discussion throughout the year about graph-based techniques and the role of software for verification, we at Cadence ended the year with a bang – last week we announced Perspec System Verifier. The customers with whom we’ve been working on this product for years tell us that this is a b... » read more

Communicate, eXecute And Translate, Oh My!

This paper describes a model-driven development approach that leverages modeling efforts to validate functionality and transform high level models into forms that are useful at the next development step. It includes an example of one company's motivations for adopting such an approach, the methodology they adopted, and the value they found in using an MDD flow. To download this white paper,... » read more

ESL Languages: Which One Is Right For Your Needs?

The question about ESL language is the right one comes up over and over again.  As customers begin to understand the benefits of modeling and analysis at the system level, they must address this question as one of the first steps in getting started.   What language should be used for ESL—SystemC, SystemVerilog, UML or M? Technically, you can create an ESL/TLM platform in any language yo... » read more