tag: University of Pittsburgh

Chip Industry Technical Paper Roundup: Jan 2
By Linda Christensen - 02 Jan, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=180 /] More ReadingTechnical Paper Library home » read more

Environmentally Sustainable FPGAs (Notre Dame, Univ. of Pittsburgh)
By Technical Paper Link - 21 Dec, 2023 - Comments: 0

A new technical paper titled "REFRESH FPGAs: Sustainable FPGA Chiplet Architectures" was published by University of Notre Dame and University of Pittsburgh. Abstract "There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous computing devices. Thus, an important challenge i... » read more

Chip Industry’s Technical Paper Roundup: Dec 5
By Linda Christensen - 05 Dec, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=171 /] More ReadingTechnical Paper Library home » read more

Chiplets For Generative AI Workloads: Challenges in both HW and SW
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets" was published by researchers at University of Pittsburgh, Lightelligence, and Meta. Abstract "Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous c... » read more

Technical Paper Round-Up: Aug 23
By Linda Christensen - 23 Aug, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

Technical Paper Round-up: May 17
By Linda Christensen - 17 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=27 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a go... » read more

Novel H2H mapping algorithm with both computation and communication awareness
By Technical Paper Link - 06 May, 2022 - Comments: 0

New research paper "H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness" from University of Pittsburgh, Georgia Tech. Abstract: "The complex nature of real-world problems calls for heterogeneity in both machine learning (ML) models and hardware systems. The heterogeneity in ML models comes from multi-sensor perceiving and multi-task lear... » read more

Power/Performance Bits: Feb. 18
By Jesse Allen - 18 Feb, 2020 - Comments: 0

Cryogenic memory Researchers at Oak Ridge National Laboratory demonstrated a new cryogenic memory cell circuit design based on coupled arrays of Josephson junctions. Such a memory could help enable exascale and quantum computing. The cells are designed to operate in super cold temperatures and were tested at just 4 Kelvin above absolute zero, about minus 452 degrees Fahrenheit. At these col... » read more

3 Ways To Reload Moore’s Law
By Michael Watts - 18 Jun, 2015 - Comments: 1

The electronics revolution has been enabled because the cost and power per transistor has decreased 30% per year for the last 30 years — a fact usually associated with Moore's Law. This has been accomplished by simply reducing the transistor size while offsetting increased costs of equipment and mask levels, and by increased productivity from improved yield, throughput and wafer size. This... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy