Working With Custom Checkers In Dynamic Simulation Of Low Power Designs


Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from ta... » read more

Could DVCon Be Better?


DVCon is undoubtedly the best conference in the industry if your interest is functional verification. In the past, it has also had a slant toward design. The focus is quite simply based on the standards activity going on within [getentity id="22028" e_name="Accellera"], the EDA industry's body that turns problems into solution in a short space of time. As those standards mature, they are handed... » read more

2017: Tool And Methodology Shifts


As the markets for semiconductor products evolve, so do the tools that enable automation, optimization and verification. While tools rarely go away, they do bend like plants toward light. Today, it is no longer the mobile phone industry that is defining the direction, but automotive and the Internet of Things (IoT). Both of these markets have very different requirements and each creates their o... » read more

Power Management Vs. State Machines


In the last several years, contemporary SoCs (systems-on-a-chip) have become very complex silicon solutions. They now consist of hundreds of millions of gates, 100 or more discrete Semiconductor Intellectual Property (SIP) blocks, high-speed data channels, megabytes of volatile and non-volatile embedded memory, increasing amounts of analog/mixed signal functionality, multiple CPU cores and mult... » read more

Multiple Dimensions Of Low-Power Verification With Portable Stimulus


There is little doubt that designing for low power is one of the biggest challenges for today’s system-on-chip (SoC) devices. The need to minimize power consumption is clear for the vast array of portable electronic devices that we use every day. Consumers expect most of their gadgets to last multiple days before they require recharging, and low-power design is the key to extending battery li... » read more

The Fundamental Power States For UPF Modeling And Power Aware Verification


The IEEE 1801-2015 specifies the new semantics of power states through the ‘add_power_state’ UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concepts are actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states. In ... » read more

The Time Dimension Of Power


Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

Toward Real-World Power Analysis


The expansion of emulation into new fields, rather than just functional verification, is making it possible to do power analysis over longer spans of time. The result is a fast and effective way to analyze real-world scenarios. This is a new field, and it marks a new use of this technology. While it is still evolving, several ideas have surfaced about the best methodology and the best way to... » read more

Power Limits Of EDA


Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Mixed-signal/Low-power Design


Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

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