tag: variation

Challenges Of Testing Advanced Packages
By Ed Sperling - 19 Sep, 2023 - Comments: 0

The number of things that can wrong in assembly and test increases as more chips are added into a package. Testing is the usual guarantor of a reliable device, but in an advanced package there are all sorts of new issues — more contacts, different handling requirements, the necessary thermal conditions for test, and variation within the package. George Harris, vice president of global test se... » read more

Accelerating Monte Carlo Simulations For Faster Statistical Variation Analysis, Debugging, And Signoff Of Circuit Functionality
By Cadence - 23 Aug, 2023 - Comments: 0

Over the years, semiconductor process nodes have been scaled aggressively, with device dimensions now approaching below 5nm. This, along with lower device operating voltages and currents, has allowed modern integrated circuits (ICs) and system-on-chip (SoC) designs to integrate more devices in a smaller chip area without compromising on lower power consumption and optimal performance. However, ... » read more

Managing Voltage Variation
By Barry Pangrle - 07 Aug, 2023 - Comments: 0

Engineers make many tradeoffs when designing SoC’s to better meet design specifications. Power, Performance and Area (PPA) are the primary goals and all three impact the cost of the implementation. For example, higher power and performance can both require more expensive packaging for power and signal integrity as well as cooling. The larger the die area the fewer die per wafer which drives u... » read more

Journey From Cell-Aware To Device-Aware Testing Begins
By Laura Peters - 06 Jun, 2023 - Comments: 0

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

What Designers Need To Know About GAA
By Brian Bailey - 13 Apr, 2023 - Comments: 0

While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Taming Corner Explosion In Complex Chips
By Brian Bailey - 23 Feb, 2023 - Comments: 0

There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

Silent Data Corruption
By Ed Sperling - 12 Dec, 2022 - Comments: 0

Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Variability Becoming More Problematic, More Diverse
By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Making Chips Yield Faster At Leading-Edge Nodes
By Ed Sperling - 30 Nov, 2022 - Comments: 0

Simulation for semiconductor manufacturing is heating up, particularly at the most advanced nodes where data needs to be analyzed in the context of factors such as variation and defectivity rates. Semiconductor Engineering sat down with David Fried, corporate vice president of computational products at Lam Research, to talk about what's behind Lam's recent acquisition of Esgee Technologies, ... » read more

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