Deterministic ICE App Tackles ICE Limitations

Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out. However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. W... » read more

Five Steps To Quality CDC Verification

With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verifi... » read more

Safety-Critical Chips Have A Premium Verification Cost

While the market opportunities in the automotive space may be exciting, the economics are staggering as consumers demand all kinds of new technologies: low power, safety-critical verification, Internet of Things — and they want it all at an incremental price of zero dollars over the actual value of the product. This can make business decisions about even entering a market a delicate balan... » read more

Choosing Verification Engines

Emulation, simulation, FPGA prototyping and formal verification have very specific uses on paper, but the lines are becoming less clear as complexity goes up, more third-party IP is included, and the number of use cases and interactions of connected devices explodes. Ironically, the lines are blurring not for the most complex SoCs, such as those used in smart phones. The bigger challenge app... » read more

The Real Differences Between HW And SW

How many times have we heard people say that hardware and software do not speak the same language? The two often have different terms for essentially the same thing. What hardware calls constrained random test is what software people call fuzzing. Another one recently caught my eye in a conversation with Jama Software, a Portland software company that has made a name for itself in requiremen... » read more

Using Formal Verification To Prevent Catastrophic Security Breaches

The news of last week’s Yahoo hack that affected 500-million or so users sent shock waves of anxiety far and wide. It’s not clear yet how the massive data breach occurred or through what means the hackers accessed the network. It could be the chips that drive the network, often vulnerable to attacks on their operational integrity. It’s no surprise, then, that semiconductor companies ar... » read more

Rethinking Verification For Cars

As the amount of electronic content in a car increases, so does the number of questions about how to improve reliability of those systems. Unlike an [getkc id="76" kc_name="IoT"] device, which is expected last a couple of years, automotive electronics fall into a class of safety-critical devices. There are standards for verifying these devices, new test methodologies, and there is far mo... » read more

Gaps In The Verification Flow

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

The 2016 Wilson Research Group Functional Verification Study

I am writing a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Some of the more interesting trends in our 2016 study are related to F... » read more

Managing Power Without Impacting Design Intent

The good news is that there are many techniques available to optimize power in your design. The not-so-good news? Many of these power management techniques also create new complexities in the physical and functional behavior of electronic designs. Fortunately, there’s more good news: implementing a power-aware verification methodology can help you verify power optimization without detracti... » read more

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