Addressing The Complex Challenges In Low-Power Design And Verification


This paper provides a comprehensive analysis of various complex debug problems faced in low-power design and verification. By using relevant examples it demonstrates how these issues can be either avoided or easily solved. We will also highlight some of the common pitfalls that low-power designers can avoid, which otherwise can lead to complex low-power issues that are difficult to debug at lat... » read more

Design Challenges Of Next-Generation AESA Radar


Phased-array antennas, first used in military radar systems, are gaining in popularity for a variety of applications with new active electronically-scanned arrays (AESAs) being used for radar systems in satellites and unmanned aerial vehicles. As these systems are deployed, meeting size and performance requirements are critical. To support AESA radar development efforts, electronic design autom... » read more

Finally, A Painless Solution For Analog Verification Management


Usually, teams manage analog simulations manually or they use complex and expensive tools that require intricate setup and proprietary test plans before they can be deployed. What teams need is an easy way to manage analog verification in order to track the large number of simulations for each project. Tracking simulation results at all levels for each team member and project managers requires ... » read more

Emulating Systems Of Systems


System design is all the craze these days. I have been in notably more discussions recently about how one can verify systems of systems. Does an airplane or a car lend itself to an array of emulators? Are multiple abstractions needed? How can design teams span electrical, mechanical, and thermal—as well as analog and digital—effects? Do companies need to re-organize to deal with system desi... » read more

How Much Verification Is Necessary?


Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Using Formal To Verify Safety-Critical Hardware For ISO 26262


Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. These sophisticated features are made possible by increasingly complex electronic systems—systems that... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Data Management For Mixed-Signal Designs


Software teams have long used version control and data management systems and they have become an integral part of a so ware development environment. Practically, no significant software project is started without a software data management system and methodology in place. There are a variety of solutions, typically referred to as Software Configuration Management (SCM) systems, to choose from ... » read more

Ignoring Anomalies


Everyone has been in this situation at some point in their career—you have a data point that is so far out of the ordinary that you dismiss it as erroneous. You blame the test equipment, or the fact that it is Friday afternoon and happy hour started 10 minutes ago. In most cases it may never happen again and nobody will ever notice that you quietly swept it under the rug. But in doing so, ... » read more

Verification Unification


Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with the recently released early adopter's draft of Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e... » read more

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