tag: verification

Advanced Design Debug Demands Integrated Verification Management
By Robert Ruiz - 14 Dec, 2023 - Comments: 0

Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced techniques such as 2.5D and 3D multi-die systems and emerging technologies such as wafer-scale integration pack even more transistors and functionality into a single device. This situation has created... » read more

Demystifying Mixed-Signal Simulation For Digital Verification Engineers
By Cadence - 13 Dec, 2023 - Comments: 0

The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs have emerged as the dominant technology, therefore requiring traditional analog and digital methodologies to be enhanced. A mixed-signal design offers many advantages, including boosted performance, r... » read more

How The Productivity Advantages Of High-Level Synthesis Can Improve IP Design, Verification, And Reuse
By Cadence - 06 Dec, 2023 - Comments: 0

Engineering teams are under more pressure than ever before—systems on chip (SoCs) are growing more complex and design schedules are increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of ... » read more

The Good Old Days Of EDA
By Brian Bailey - 30 Nov, 2023 - Comments: 5

Nostalgia is wonderful, but there is something about being involved in the formative years of an industry. Few people ever get to experience it, and it was probably one of the most fortuitous events to have happened in my life. Back in the early '80s, little in the way of design automation existed. There were a few gate- and transistor-level simulators, primarily for test and a few 'calculators... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges
By Kunal Chhabriya - 02 Nov, 2023 - Comments: 0

In PCI Express (PCIe), a high-speed serial computer expansion bus standard, Compliance mode is used for testing the transmitter and interconnect to assess if their voltage and timing are compliant with the specification. This testing happens in the Polling Compliance state which is a dedicated state for Compliance testing in the Link Training and Status State Machine (LTSSM). In Unraveling the... » read more

A New Architecture And Verification Approach For Hardware Security Modules
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “The K2 Architecture for Trustworthy Hardware Security Modules” was published by researchers at MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) and New York University. Abstract: "K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation ... » read more

The Limits Of AI-Generated Models
By Brian Bailey - 26 Oct, 2023 - Comments: 2

In several recent stories, the subject of models has come up, and one recurrent theme is that AI may be able to help us generate models of a required abstraction. While this may be true in some cases, it is very dangerous in others. If we generalize, AI should be good for any model where the results are predominantly continuous, but discontinuities create problems. Unless those are found and... » read more

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