The Trust Burning Debug Cycle From Hell

As bad as The Trust Burning Debug Cycle From Hell sounds, it’s worse than you think. Most of us don’t realize it exists. In my first 10 years as a hardware developer I wrote code like it could never exist! But then came the realization. It’s a cycle that preys on us all. It tempts me constantly. Most of us in hardware development are used to seeing bugs as annoyances at a minimum, thou... » read more

Making Verification Easier

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

Why I See C In SCE-MI

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Debug Becomes A Bigger Problem

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

Will The Chip Work?

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Can IP Integration Be Automated?

What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

Top 15 Integrating Points In The Continuum Of Verification Engines

The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

HDMI 2.0 Design And Verification Challenges

High-Definition Multimedia Interface (HDMI) is an audio/video (A/V) trans- mission protocol, which is omnipresent in consumer electronics, personal computing, and mobile products. Modern-day requirements of big screen resolutions, 3D, and multi-channel/multi-stream audio have pushed display devices to use a completely digital, high-speed transmission media, requiring a multi-layered protocol li... » read more

HDMI 2.0 Design And Verification Challenges

HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

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